Leading a talented team, the hybrid ASIC Design Verification Engineer will develop and execute verification strategies for AI inference ASICs, collaborating with design and architecture teams to ensure functional correctness and performance. Key Responsibilities Develop and execute verification strategies for AI inference ASICs Define and implement comprehensive test plans and verification methodologies Lead the development of verification environments using SystemVerilog UVM Required Qualifications Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field 8+ years of experience in ASIC verification Expertise in SystemVerilog UVM and simulation tools Strong knowledge of verification planning and testbench development Experience with industry-standard EDA tools (Cadence, Synopsys, Mentor Graphics)
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